The tremendous progress in the development of integrated circuits (ICs; chips, microchips, electronic circuits etc.) over the last decades has scaled down the relevant scales for design structures to the submicron and even to the nanometer regime. Hereinafter, “integrated circuit”, e.g., is related to digital integrated circuits that contain a set of digital electronic circuits including logic gates, flip-flops, multiplexers and other circuits. Such small structures, on one hand, in combination with an increase in the complexity of the total design, on the other, makes it a very challenging task for semiconductor companies to reduce the defects in their chips. In order to reduce the development costs of integrated circuits, companies subject their products to scan tests. The smaller the structures get, the more difficult it is to obtain a high test coverage, which, in turn, implies a higher quality of the product. Submicron and nanometer structures not only do suffer from functional defects (e.g., shorts or opens in the device interconnect), but, in particular, from timing-related delay defects (such as high-impedance shorts, in-line resistance, cross-talk between signals). While the former can effectively be detected in static tests (e.g., stack-at fault model and IDDQ fault model) the latter can be accessed only through at-speed tests. Available automatic test pattern generation (ATPG) tools are able to deal with delay defects. Typically, at-speed fault models (e.g., transition delay fault models using the launch-off-shift or skewed-load method, transition delay fault models using the launch-off-capture or broadside method, path delay fault model, to name some of frequently used at-speed tests) consist of two parts: during the first part, a logic transition to be verified is launched, while in the second part the response is captured one application period after (hereinafter referred to as “capture cycle”), the application period being, e.g., identical to the clock period.
Any of the aforementioned test models become ineffective and lead, consequently, to a low test coverage, once a test circuit of an integrated circuit includes uncontrollable or partially controllable logics. Many chip manufacturers incorporate in their chip design, e.g., so-called intellectual property (IP) modules, the behavior of which is only well known during functional operation, while it is not during test operation. Such uncontrollable or partially controllable logics may lead to uncontrollable or partially controllable output signals during test operation, forcing the number of accessible test vectors to be strongly constrained, leading to a low test coverage. In the previous art related to structural at-speed delay-fault tests, such an issue has not yet been addressed.